1. Field of the Invention
The present invention relates to technique regarding a duplexed system for an operation processor (hereinafter referred to as “CPU”) used in a plant control and the like.
2. Description of the Related Art
Conventionally, CPUs used for a plant system control or the like are duplexed or multiplexed so as to provide a control without stopping the plant system even when a trouble occurs in a primary CPU, or to allow a secondary CPU to update a control program without stopping the plant system during the program updating operation, thereby to enhance availability of the system. On such an occasion, a quick CPU switch-over is required when a program is updated or a problem occurs.
In order to provide such a quick switch-over operation, it is required that plural CPUs acquire control information from a control target in an identical manner among the CPUs. In order for plural CPUs to acquire control information in an identical manner, it has been known that each CPU individually acquires control information from a control target, or that one of duplexed CPUs snoops memory data on the other CPU to acquire control information of interest, as disclosed in JP H09-305424 and JP H09-245008.
However, in the above conventional case, since the memory data frame is snooped from a line coupling a primary CPU to the memory data, and a secondary CPU acquires the memory data frame via an equalization bus using parallel buses that are weak against noise, this technique is not suitable to a long distance data transmission. Addition to the above difficulty, data frame to be snooped is usually stored on the primary CPU, so that the primary CPU and the secondary CPU cannot process the data synchronically, which may cause time delay and sacrifice response speed of the system, and a function of updating a program without stopping the plant system is additionally required, which makes functions of the system more complicated.
In order to address the above difficulties, the present invention has an object to provide a duplexed CPU control system that is strong against noise even though a distance between a primary CPU and a secondary CPU becomes longer, without scarifying response speed of a system, providing a quick switch-over between the primary and secondary CPUs at the time of updating a program or a problem occurrence.
The present invention has another object to provide a duplexed CPU control system that updates a control program for controlling a plant without stopping a plant system, with no requiring an additional function to perform a program updating.
Other features and advantages of the present invention will become more apparent from the following detailed description of the invention when taken in conjunction with the accompanying exemplary drawings.